ARM, while ostensibly a RISC architecture, nevertheless has block move instructions, single instructions capable of loading and storing (respectively) multiple registers. The LDMIA (load multiple, increment after) instruction permits any combination of ARM’s (Thumb) 16 registers to be loaded from consecutive memory locations while the STMDB (store multiple, decrement before) instruction stores any combination of the registers to consecutive memory locations. (There are also LDMDB and STMIA instructions among others.) The registers do not need to be contiguous. The instruction below loads registers r3, r4, r5, and r9 from the memory location pointed to by r0, r0+4, r0+8, and r0+12 respectively. Then increments r0 by 16 (4 word of 4 bytes each).


LDMIA ro, {r3, r4, r5, r9}


Required:

a. Identify a likely application for this capability. What would the LDMIA instruction be used for? What would the STMDB instruction be used for?

b. Ignoring any additional data path requirements, could this instruction be implemented on MIPS? Why or why not?